Conventionally, a method called source shared driving (SSD) has been used as one method for driving liquid crystal display devices. A liquid crystal display device includes: a plurality of scanning signal lines; a plurality of data signal lines extending orthogonally to the plurality of scanning signal lines; and pixels provided two-dimensionally at intersections of the above signal lines in a matrix pattern. According to the SSD method, each set of data signal lines is driven by using source signals time-divided by a data output circuit shared by the set of data signal lines.
FIG. 10 is an equivalent circuit diagram illustrating an arrangement of a conventional active matrix liquid crystal display device driven by the SSD method. As illustrated in FIG. 10, the conventional liquid crystal display device includes: a data line driving circuit (source driver) 101; a gate line driving circuit (scanning signal line driving circuit) 102; a data line selection circuit 103; and a display section 109.
The display section 109 includes a plurality of gate lines (m gate lines) GL1 through GLm as scanning signal lines; a plurality of data signal lines (n data signal lines) (source lines) DL1 through DLn intersecting orthogonally with the plurality of gate lines; and a plurality of pixel forming sections (m×n pixel forming sections) each including a pixel switching element 105 and a liquid crystal capacitor 106. The pixel forming sections are provided at respective intersections of the plurality of gate lines GL1 through GLm and the plurality of data signal lines DL1 through DLn. The pixel forming sections are arranged in a matrix pattern so as to form a pixel array.
In each of the pixel forming sections, the pixel switching element 105 has (i) a gate terminal connected to one of the plurality of gate lines, (ii) a source terminal connected to one of the plurality of data signal lines, and (iii) a drain terminal connected to a pixel electrode. Each of the pixel forming sections further includes a counter electrode that is common to all the pixel forming sections and facing each pixel electrode. Each of the pixel electrodes and the counter electrode sandwich a liquid crystal layer, so that a liquid crystal capacitor 106 serving as a pixel capacitor is formed.
Each pixel electrode is supplied with a potential corresponding to an image to be displayed, by means of respective operations of the data line driving circuit 101 and the gate line driving circuit 102, whereas the common electrode is supplied with a predetermined potential from a counter electrode control section 108 (not shown). This voltage application controls an amount of light transmitted through the liquid crystal layer, thereby causing an image display to be carried out. For controlling the amount of transmitted light by applying voltages to the liquid crystal layer, the display section further employs polarizing plates (not shown).
In the active matrix liquid crystal display device driven by the SSD method (see FIG. 10), the plurality of data signal lines DL1 through DLn are connected to their respective gate switching elements 104 and then, every three data signal lines out of the plurality of data signal lines DL1 through DLn are bundled into a set. The set of three data signal lines is further connected to one of output signal lines D1 through Dn/3 of the data line driving circuit 101.
Each of the gate switching elements 104 is connected to the data line selection circuit 103 via one of data line selection lines GLa, GLb, or GLc. The data line selection circuit 103 controls an ON/OFF state of each of the gate switching elements 104. This causes every three data lines forming a set to be sequentially connected to a corresponding one of the output signal lines. For example, the data signal lines DL1, DL2, and DL3 form a set and are connected to the output signal line D1. The control of the ON/OFF state of each corresponding gate switching element 104 by the data line selection circuit 103 causes the data signal lines DL1, DL2, and DL3 to be sequentially and electrically connected to the output signal line D1.
The above is described in more detail below. The data signal lines DL1, DL2, and DL3 are connected to their respective columns of pixels, each of which columns corresponds to one of three primary colors, i.e., red (R), green (G), and blue (B), constituting a display color. Each set of such three data signal lines corresponding to R, G, and B constituting a single display color is driven by a corresponding data output circuit (not shown) which is provided in the data signal line driving circuit 101 and which is common to the set of the data signal lines corresponding to R, G, and B. Each data output circuit supplies data to a corresponding set of data signal lines in the order of R, G, and B. For the purpose of not only increasing a drive rate but also securing a certain time period necessary for each data signal line to write a data signal to corresponding pixels, data signal lines that are in the respective sets and correspond to one color are driven simultaneously. Specifically, among all the data signal lines in the respective sets connected to the output signal lines D1 through Dn/3, data signal lines corresponding to R are first driven simultaneously; data signal lines corresponding to G are next driven simultaneously; and data signal lines corresponding to B are finally driven simultaneously.
In a case where the liquid crystal display device is driven by the above method, the counter electrode 107 is supplied with a voltage at a constant value while one gate line is active. In order to prevent image burning in liquid crystals, a signal (hereinafter referred to as “a COM signal”) for driving the counter electrode 107 normally has two potentials alternately outputted. In other words, an inversion driving is normally carried out. Specifically, the counter electrode 107 is supplied with a voltage while a given gate line is active, whereas the counter electrode 107 is supplied with an inversed voltage of the above voltage while another gate line adjacent to the above given gate line is active.
FIG. 11 is a timing chart illustrating the inversion driving of the counter electrode in the liquid crystal display device driven by the SSD method. As illustrated in FIG. 11, the gate lines GL1 through Gm are sequentially supplied with scanning signals. Specifically, the gate lines GL1, GL2, . . . Gm are sequentially selected by the gate line driving circuit 102, and are thereby supplied with scanning signals from the gate line driving circuit 102. This causes each pixel switching element 105 connected to a selected gate line to have a gate turned ON. This causes each of the pixel switching elements 105 to be in an active state in which a source signal (i.e., data signal) can be supplied to a corresponding pixel electrode.
Further, as illustrated in FIG. 11, while each of the gate lines GL1 through Gm is selected, the data line selection lines GLa, GLb, and GLc are sequentially supplied with data line selection signals. The data line selection line GLa is connected to data lines corresponding to R pixels; the data line selection line GLb is connected to data lines corresponding to G pixels; and the data line selection line GLc is connected to data lines corresponding to B pixels. Thus, a sequential supply of data line selection signals to the data line selection lines GLa, GLb, and GLc causes the respective data lines, each of which is connected to pixels corresponding to one of R, G, and B, to be sequentially selected.
For example, in FIG. 11, while the gate line GL1 is selected, the data line selection lines GLa, GLb, and GLc are sequentially supplied with data line selection signals. When a data line selection signal is supplied to a given data line selection line, each gate switching element connected to the given data line selection line is caused to have a gate turned ON. This allows a data signal from a corresponding output signal line to be supplied to each data line connected to such a switching element that is in an ON state. This consequently causes data signals from respective output signal lines to be sequentially supplied to corresponding data lines for respective columns of pixels each of which columns corresponds to one of R, G, and B.
Further, as illustrated in FIG. 11, while each of the gate lines GL1 through Gm is selected, the output signal lines D1 through Dn/3 are supplied with data signals simultaneously. Each output signal line is supplied with data signals for R, G, and B by time division. For example, in FIG. 11, while the gate line GL1 is selected, the output signal line D1 is supplied with data signals R11, G12, and B13 by time division; the output signal line D2 is supplied with data signals R14, G15, and B16 by time division; and the output signal line Dn/3 is supplied with data signals R1(n−2), G1(n−1), and B1n by time division.
Each of the output signal lines D1 through Dn/3 is supplied with data signals for R, G, and B by time division at timings synchronizing with respective timings at which the data lines for the respective columns of pixels, each of which columns corresponds to one of R, G, and B, are sequentially selected by the above data line selection signals.
For example, in FIG. 11, while the gate line GL1 is selected, the data line selection lines GLa, GLb, and GLc are sequentially supplied with data line selection signals. The data line selection lines GLa, GLb, and GLc are supplied with the data line selection signals at respective timings each of which synchronizes with a corresponding one of timings at which each of the output signal lines D1 through Dn/3 is sequentially supplied with data signals for R, G, and B by time division.
This makes it possible to supply (i) a data signal for R to each data line for pixels corresponding to R, (ii) a data signal for G to each data line for pixels corresponding to G, and (iii) a data signal for B to each data line for pixels corresponding to B.
As described above, in the case where the liquid crystal display device is driven by the above method, the counter electrode 107 is supplied with a COM signal at a constant value while one gate line is active. In order to prevent image burning in liquid crystals, such a COM signal for driving the counter electrode 107 normally has two potentials alternately outputted. In other words, an inversion driving is normally carried out.
Data signals for R, G, and B are written to pixels as described below.
First, in a period in which the gate line GL1 and the data line selection line GLa are both active, respective voltage differences are produced between (i) the data signals R11 through R1(n−2) supplied to corresponding data signal lines each connected to one of the output signal lines D1 through Dn/3 and (ii) a COM signal supplied during this period. These voltage differences are respectively written to corresponding pixels (i.e., pixels corresponding to R).
Then, in a period in which the gate line GL1 and the data line selection line GLb are both active, respective voltage differences are produced between (i) the data signals G12 through G1(n−1) supplied to corresponding data signal lines each connected to one of the output signal lines D1 through Dn/3 and (ii) a COM signal supplied during this period. These voltage differences are respectively written to corresponding pixels (i.e., pixels corresponding to G).
Further, in a period in which the gate line GL1 and the data line selection line GLc are both active, respective voltage differences are produced between (i) the data signals B13 through B1n supplied to corresponding data signal lines each connected to one of the output signal lines D1 through Dn/3 and (ii) a COM signal supplied during this period. These voltage differences are respectively written to corresponding pixels (i.e., pixels corresponding to B).
The above operation causes data signals to be written to all pixels connected to a single gate line. When this writing of data signals to the pixels connected to the gate line GL1 is completed, writing of data signals to pixels connected to the gate line GL2 begins. As in the gate line GL1, the data signals, when written to the pixels connected to the gate line GL2, are sequentially written to respective sets of pixels, each of which sets corresponds to one of R, G, and B. This operation is repeated so that the remaining gate lines are also scanned in the same manner one after another in a vertical direction, until the above operation is carried out with respect to the gate line GLM. As a result, the data signals are written to the M×n pixels constituting an entire screen.
The following description deals with the line inversion driving of the COM signal. FIG. 12 is a circuit diagram illustrating a circuit for generating voltages to be applied to the counter electrode for the line inversion driving. In the line inversion driving, two potentials are alternately outputted. In the example illustrated in FIG. 12, two voltages constituting the COM signal used for the line inversion driving have a high value COMH and a low value COML.
As illustrated in FIG. 12, an inversion driving circuit 120 includes: two selectors 121a and 121b; an output buffer 122; and a resistor 123. The resistor 123 is connected to a power supply voltage and also to ground. Each of the selectors 121a and 121b is connected to the resistor 123 via a plurality of terminals, and thereby selects, from among a plurality of voltage values, a value of a voltage to be outputted. The selector 121a outputs a voltage having a selected value as COMH, whereas the selector 121b outputs a voltage having a selected value as COML. The voltages COMH and COML are supplied from the selectors 121a and 121b, respectively, to the output buffer 122. The output buffer 122 is also supplied with rectangular waves (e.g., signals each generated for a single horizontal scanning period of a gate line) in synchronization with the line inversion driving. The output buffer 122 alternately outputs COMH and COML as a COM signal in accordance with the rectangular waves supplied. This consequently causes the output buffer to alternately output COMH and COML each for each one line.
Presently, liquid crystal display devices come to have a higher quality level and there arises a growing demand for varying each of respective luminances of R, G, and B independently of the others. In view of such a demand, there have been known methods for independently controlling each of source potentials for R, G, and B.
FIG. 13 is a circuit diagram illustrating a conventional technique of independently adjusting each of source voltages for R, G, and B. In an arrangement where each of luminances of R, G, and B is not independently varied, it is required merely to select each source voltage with use of 8-bit data for displaying 256 levels of gray. Meanwhile, for displaying 256 levels of gray by independently varying each of the luminances of R, G, and B, it is required to independently select and control each of 256 levels of gray for R, 256 levels of gray for G, and 256 levels of gray for B. This requires, as illustrated in FIG. 13, an arrangement in which each source voltage is selected with use of 10-bit data.
Patent Literature 1 discloses a technique of equalizing, in consideration of luminosity, respective brightnesses of R, G, and B in a liquid crystal display device including common signal lines for respective pixel columns for R, G, and B. According to the liquid crystal display device disclosed in Patent Literature 1, common signals supplied to the respective pixel columns for R, G, and B have their respective selected-level voltages that are different from one another. In other words, different selected-level voltages are set in advance for R, G, and B, respectively, so that in a case where respective tones of R, G, and B are identical to one another, an identical brightness is visually sensed for all of R, G, and B by a viewer.